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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | IT - Software |
| Functional Area | Service / Installation / Repair |
| EmploymentType | Full-time |
Create verification test plans. Drive/Participate in discussions across various disciplines to get a clear understanding of requirements. Develop the architecture and design of the verification environment in OVM/UVM for pre-silicon RTL verification Develop/run/debug tests in SystemVerilog Mentor other engineers in using the verification infrastructure and creating test benches. Ownership of verification of block/cluster/ip level testing Actively review code created by fellow team mates. Participate in func coverage, code coverage reviews and provide/implement feedback. Should be able to support debugs on sub-system/SOC that use the IP provided. Should also be able to support post-silicon/platform failures related to the IP provided. Contribute to the development and maintenance of long term design verification strategy. Track progress of self/subteam to achieve goals timely. Provide indicators and guidance to management on issues and roadblocks on a timely basis. Be able to work with teams across geosExperience with creation of plans, schedules and cost estimates for design verification efforts. Experience in development and deployment of verification strategies and methodologies across teams and organizations. Apart from simulation, should have work experience with at least one other verification aspect like Performance modeling, Formal verification, Gate Level verification, Emulation, etc. would be a added advantage. Experience with implementation of modern verification environments that include use of constrained-random stimulus and use of functional coverage. Proficiency in SystemVerilog. Hands on experience and significant expertise with OVM/UVM is a must. Proficiency in scripting languages and utilities including Make, Perl, Python, etc. will be a bonus. Expert level knowledge of simulation tools such as VCS from Synopsys. Experience in mixed signal IP design verification is a plus with protocols such as PCI-Express, SATA, USB, Display I/O, MIPI, Ethernet, etc. and AMBA, JTAG, PIPE, etc. is desired Should be able to contribute as IC or technically leading a group of team as per requirementQualificationsCandidate must have a BSEE or MSEE with 4-12 years of domain experience including hands-on verification experience using SystemVerilog and OVM/UVM Strong understanding of engineering design principles Working knowledge of one or more of the following interfaces: PCI-Express, SATA, USB, Display I/O, MIPI, Ethernet and and AMBA, JTAG, PIPE, etc. is desired Proven track record in ASIC verification from environment development to tests development and debug support Excellent written and verbal communication skillsInside this Business GroupIP Engineering Groups (IPG) vision Build IPs that power Intels leadership products and power our customers silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intels silicon design process. IPGs guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.,
Keyskills :
mixed signalcode coveragertl verificationasic verificationcommercial modelssystem integratorsengineering designbehavioral trainingformal verification