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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | IT - Software |
| Functional Area | Engineering Design / Construction |
| EmploymentType | Full-time |
Highly proficient in RTL design using Verilog/System Verilog with experience in high speed DSP datapath designs as well as control FSMs for PPA optimizations Deep knowledge in Synthesis, DFT and STA flows including .lib generation for hard macros as well as good exposure to PNR handoffs and design fixes to meet timing Experience of working in time domain signal processing blocks interfacing high speed mixed-signal blocks such as data converters, PLLs is highly desired Good knowledge of high Speed Serdes PHYs such as USB, PCIe, Ethernet (10G/40G/100G/200G/400G etc ) is preferred Involved in delivery of complex DDR/Serdes IP s to customers and support Closely working with analog teams for algorithm development and Silicon validation teams to bring-up Silicon as well as fine tune and debug performance issues at high speed Good working knowledge SOCs involving DSPs / uC development for embedded systems Proficient in Scripting languages such as Perl and working with Firmware team for development in C We re doing work that matters. Help us solve what others can t.,
Keyskills :
systemssiliconadministrationvalidationdeliverypnrmanagementmacroseducationcommunicationdftdspsenglishperlevelopmentembeddedalgorithm