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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | Manufacturing |
| Functional Area | Engineering Design / Construction |
| EmploymentType | Full-time |
The RF Design Enablement Test-site layout Engineer is responsible for working the Design Enablement and modeling teams to develop best in class RF enablement for GLOBALFOUNDRIES customers. Included within this scope test-chip design for technology qualification and related development, maintenance methods & systems to ensure quality technical outcomes of the deliverables.Essential Responsibilities:- Delivery of test-site design to support technology qualification- Interpret process design rules, specifications (p-cell, floor-plan) for device/macro creation- Closely engage with compact modelers, PDK developers and ensure specifications implemented ahead of test-chip tapeout- Through physical verification / validation of all device/macro components of PDK test-site before tape-out- Automate PDK Test-site development & verification process- Closely engage with compact modelers, designers and ensure specifications implemented ahead of test-chip tape-out- Collaboration with PDK Library, technology development, test-site layout & developers across global organization- Good communication and interpersonal skills and the ability to work effectively in a cross-functional team environment- Create, update / track ongoing development work progress & add usage guidesKey focus is to maintain high quality PDK enablement for GFs RFBU Foundry technologies and clients. A person in this role may interact with external Foundry Clients, Electronic Design Automation (EDA) vendors., Education/Experience:- B.Tech / M.Tech in Electronics Engineering or VLSI- Direct experience in EDA tools Cadence Virtuoso, Mentor Calibre- Semiconductor device knowledge- Direct experience in custom layout development & verification- Experience in Shell, Perl, Cadence SKILL & python programmingPreferred Qualifications:- 2+ years of direct work experience in custom layout development & verification.
Keyskills :
eda toolsprocess design semiconductor deviceproject administration technology developmentelectronics engineering design automatio