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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | Manufacturing |
| Functional Area | R&D / Product Design |
| EmploymentType | Full-time |
As a dynamic organization, we are always seeking to hire exceptional talent to join some of the brightest inventors and engineers in the world to explore their passions to develop products that have real life impact. As well, Rambus benefits are among the most comprehensive and competitive in Silicon Valley. Responsibilities Define the architecture of SERDES PHY IPs, its major blocks Responsible to develop the architecture and create specification for clocking, ASIC interface, pin-outs, floor plans, functionalities to support the protocol/ system level requirements, digital/ analog/ firmware interface and partitions, calibration and other algorithm definition, test/ debug logic etc Experience in understanding/ defining algorithms to measure physical quantities (like phase, frequency, ISI, slew rate, duty cycle etc. ) and fine tuning of the analog blocks is desirable Work with cross-functional teams and technical experts in various geographies to define and align scope of the IPs Support marketing on presales activities technically Be the interface to the customer in technical interactions, feasibility analysis, interoperability definitions and tracking Understand and disseminate applicable standards and its relevance in a given project to the team Provide definitions of scope and review the plans of verification team Work with the system engineering team for Silicon bring up and Characterization. Qualifications MS/ M-Tech degree in electronics/ VLSI and in exceptional cases B. E/ B-Tech in electronics engineering with 12 years of relevant experience needed. (The experience profile will depend on the job level of the position) The candidate should have prior experience of working on digital designs including RTL development, timing closure and lab debug of Silicon Experience in designing serial links such as PCIE/ USB/ Ethernet/ CEI6 etc High level understanding of LEQ, PLL, CDR, DFE, CMU is desirable Experience on mixed signal designs is desirable Experience in architecture or micro-architecture development Experience working with customers and cross-functional teams Experience working in leading R&D and future technology development projects is desirable. The position requires good written & verbal communication skills as well a strong commitment and ability to work in cross functional and globally dispersed teams. Rambus offers a competitive compensation package, which includes a strong base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program and gym membership. Rambus creates cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting. Our chips, customizable IP cores, architecture licenses, tools, services, training and innovations improve the competitive advantage of our customers. We collaborate with the industry, partnering with leading ASIC and SoC designers, foundries, IP developers, EDA companies and validation labs. Our products are integrated into tens of billions of devices and systems, powering and securing diverse applications, including Big Data, Internet of Things (IoT), mobile, consumer and media platforms.,
Keyskills :
java framework linux javascript igdata mixedsignal systemengineering communicationskills rtldevelopment timingclosure developmentp floorplans verbalcommunication internetofthings feasibilityanalysis