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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | IT - Software |
| Functional Area | Engineering Design / Construction |
| EmploymentType | Full-time |
Position Description: The position is part of SVG Product Engineering team focussed on SW bring-up solutions using Cadence Palladium emulation and FPGA prototyping solution and virtual / hybrid model. The position requires an experienced engineer passionate about diagnosing verification problems systematically to improve verification throughput to verify and debug cutting-edge SOCs, System ICs, and complex IPs as part of early HW-SW bring-up. The position also requires bring-up and debug of Software (Bare-metal, Operating systems) on complex SoC/Systems and analysing and improving tool performance for these use-cases. The PE plays a key role in defining, validating and deploying Cadence s products and solutions by actively engaging with customers and field engineers. This will involve working with leading semiconductor and system companies to understand their use-cases, come up with innovative solutions (working with extended team) to address their most challenging problems and deploy the same at customers working with field engineers.Position Requirements: This position requires a BS-EE/CE or MS-EE/CE with 10 years in the EDA / verification industry, use of verification tools and a strong knowledge base of the verification and performance analysis of complex digital designs. Requirements include:Strong knowledge of simulation and verification tools, with proven expertise in processor based emulation systems a plus Strong knowledge of how to debug designs, with debug in processor based emulation / acceleration platforms a plus Strong knowledge and direct experience in simulation acceleration methodologies. Virtual acceleration technology and Hybrid platforms experience for IP/SoC environments is a big plus. Strong knowledge in FPGA prototyping and SW bring-up is big plus Strong knowledge in building/debugging SC models and SW bring-up on virtual/hybrid platforms is a big plus Strong knowledge on improving verification throughput by identifying and addressing compile and run time improvements for SoC verification flows is big plus Proven expertise in supporting customers (in HW / FW and SW based systems a plus) Technical expertise in RTL Design and functional verification using High Level Verification languages such as UVM (SystemVerilog or Specman e ) or C/C Capability with scripting in languages like Perl or TCL and shell scripting Experience in advocating for customer features, including emerging verification methodologies, in an already proven SW/HW platform, taking care in understanding the effects of new features on existing user environments Strong interpersonal relationship building across different groups within and external to the BU, with a strong focus on customer product usage advocacy. Ability to distil low level technical information and create summary material for reporting to executive staff training collateral development, including white papers and presentations for field teams and early adaptors Ability to travel occasionally for up to two weeks at a time for internal training or customer project supportWe re doing work that matters. Help us solve what others can t.,
Keyskills :
rtl designwhite papersstaff trainingknowledge baseshell scriptingsoc verificationfpga prototypingproduct engineeringperformance analysis