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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | Manufacturing |
| Functional Area | R&D / Product Design |
| EmploymentType | Full-time |
Job Profile R&D Engineer IC Design 5 Memory Design Validation We are looking for energetic and passionate memory design validation engineers to join our Central Engineering Group and be part of an elite memory team responsible for the development of memory compilers and custom macros of all types on the bleeding edge of process technology. Typically requires a minimum of 9+ years of relevant experience and a Master in Electrical Engineering. Job Description Summary Contribute/Lead towards Memory Design Validation of SRAM, Multi-Ports, Register File, TCAM, and ROM memory compilers as well as custom macros in 7nm and other cutting edge process technologies Job Description Contribute/Lead towards Memory Design Validation of all types of custom memory macros and memory compilers Perform functional verification, root cause design discrepancies, and help resolve them Perform signal integrity analysis, identify design weaknesses, and propose possible solutions to address them Perform transistor level simulations to check for any Power Up or Lock up issues and help resolve them Perform EM/IR analysis/simulations and evaluate impact on timing and internal margins Perform transistor level simulations to validate timing and internal margins, identify timing characterization holes, and help resolve them Perform various QA and validation checks to ensure accurate timing and power models Develop scripts to automate verification flow and data analysis Support silicon debugs and correlation to spice models Collaborate with key memory designers to codevelop and improve the memory characterization and validation flow Coordinate with memory design leads, modelling leads, and managers to define and execute on the memory validation plan Skill Sets Strong expertise in development of memory macros of all types and architectures Deep understanding of transistor level circuit behavior and analysis Strong understanding of the layout and their related challenges in sub nanometer process technologies Strong understanding of signal integrity, EM/IR, and reliability analysis Strong understanding of memory behavioral and physical models Strong understanding of DFT Schemes and chip level integration Proficient in running transistor level simulators, writing automation scripts, and are tools savvy Complete hands on experience in using Cadence schematic/layout editor tools Complete hands on experience with transistor level simulators, Monte Carlo variation analysis, waveform viewer tools such as; HSPICE, HSIM, XA, FineSim, XARA, nWave, waveform viewer, etc. Experience in Skill/Perl/Python Scripting is a strong plus Excellent communication, interpersonal, and leadership skills Excellent debugging skills, problem solving and logical reasoning skills Motivated, self-driven and good at multi-tasking If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.,
Keyskills :
cutting compilers leadershipskills autocad telecomequipmentdesign edge tools hspice sram integrity java espondence