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Requirement for Memory Layout Design Engineer

2.00 to 5.00 Years   Bangalore   25 Apr, 2019
sebone technologies
Job LocationBangalore
EducationNot Mentioned
SalaryNot Disclosed
IndustryIT - Hardware / Networking
Functional AreaEmbedded, VLSIHardware / Telecom Equipment Design
EmploymentTypeFull-time

Job Description

Use below JD for Memory layout requirement

  • Drawing layouts for schematics created by Design Engineers in 7nm and other FINFET Technologies
  • Experience on Memory Layout. Like RAM, ROM, SDRAM etc.
  • Good knowledge on Memory layout techniques like Area/Speed/Power optimization
  • Good knowledge on different Memory Architecture and Compilers
  • Knowledge on BIT cell, data line & Address line routing concepts
  • Effectively communicate with Design Engineers to clarify and interpret the layout requirements based on the schematics
  • Prepare layout floor-plan and review it with the Design Engineer
  • Create layouts in the Cadence Virtuoso CAD platform as per floor-plan
  • Run DRC, LVS and other verifications required by customer to ensure layout meets foundry requirements
  • Provide feedback to Design Engineers on any modifications to schematics after layouts are completed
  • Support RC-extraction, IR drop and other post-layout analysis of layouts as per Design Engineers requirements
  • Layout rework arising from quality issues identified during layout reviews without a material impact to customers product schedules.

Keyskills :
drcsdramlvsvirtuosoramcadenceromloorplanmemorydesign

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