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Job Location | Bangalore |
Education | Not Mentioned |
Salary | Not Disclosed |
Industry | Consumer Durables / Electronics |
Functional Area | General / Other Software |
EmploymentType | Full-time |
ASIC/SOC Design Technical Manager/Manager/Lead : -ASIC integration, peripherals, Bus Design, ASIC Design, RTL Design, DC/PC, LINT, PTSI, Verilog/VHDL) -Timing Constraints & Closure (PTSI, STA, Primetime) -RTL Design (Functional/Structural, Partitioning, Simulation, Regression, Modelsim, VCS, Design Compiler, Primetime, Microprocessor Architecture, Memory Coherency) -Multimedia/Camera Imaging (Image processing algorithms, ASIC Design, RTL Coding, JPEG, C/C++/SystemC, Modelsim, Synopsys DC, LEC, Spyglass) -Low Power Design (clock gating, power gating, power grids, power integrity) -IC Design Methodology (Design Methodology, Simulation Tools, Performance Modeling, Architecture to GDSII) -Interconnect Architect & Design (ASIC Design, Bus Protocols, AHB, AXI, NoC, Architecture Tradeoff Analysis, Micro-Architecture, CPU Architecture) -DDR & Cache System Micro-Architect (ASIC Design, Performance Bottleneck Analysis for interconnects & memory controller, Bus Protocols: AMBA AXI, CoreConnect, OCP) -Physical Layer Design (PHY, USB, HDMI, DDR, MIPI) -SerDes Application (PHY Layer Protocol, SerDes PHY, ASIC EDA Models, Cadence Schematics) ,
Keyskills :
rtl designrtl codingasic designdesign compilercommercial modelsbottleneck analysisnocphyedartlstausbddrlecbusvcscpuaxiahbasic