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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | Manufacturing |
| Functional Area | General / Other Software,Engineering Design / Construction |
| EmploymentType | Full-time |
Senior DFT engineer with 3 yrs experience in full chip DfT implementation and verification of scan architectures, JTAG, memory BIST, ATPG. The engineer should be well versed in Verilog/VHDL RTL coding, experienced in using Mentor DfT tools and Cadence tools. The engineer needs to have hands on experience in scan insertion, JTAG, ATPG DRC and coverage analysis, Simulation debug with timing/SDF. Should work independently with minimal support and good communication skills. The engineer should be able to debug and root cause problem in simulation failures. Should be willing to take up new challenges in the project and be a team player.,
Keyskills :
atpgdftscancoresiliconrtl codingroot causescan insertionrtliotdrcnxpjtagbistrootmobileembeddedanalysisconnectivity solutionscadence