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Senior Formal Verification

7.00 to 12.00 Years   Bangalore   02 Oct, 2020
eInfochips
Job LocationBangalore
EducationNot Mentioned
SalaryNot Disclosed
IndustryIT - Software
Functional AreaGeneral / Other Software,Sales / BD
EmploymentTypeFull-time

Job Description

  • Minimum 3 years of experience in System Verilog HVL SVA Assertions.
  • Must have executed at-least 3 SoC/IP Formal Verification signoff projects
  • Must have used Synopsys VC Formal , Cadence Jasper or Questa Formal Tools comprehensively
  • Hands on experience of developing Formal SV assertion/checkers, coverage register, regressions.
Functional Checks/Assertions based Property coding to verify RTL Structures Data Path, Security, Register, Functional Safety and X Prorogation Verification Connectivity Checks on IP/SoC connections Fault Analysis using Formal Testbench Analyzer Formal Coverage and Regressions Management Role
  • At-least 2 years of experience in handling team of 2 to 5 engineers.
  • Support/Mentor new team in learning Formal Verification techniques and tools usage
  • Define/derive Scope, Estimation, Schedule and Deliverables of proposed work.
  • Assure compatibility of resources, tools, platform
  • Work with customers through acceptance of deliverables.
  • Effectively manage team members through coaching and mentoring and provide guidance and career planning to team-members.
  • Ensure customer satisfaction.
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Keyskills :
system verilogfault analysiscareer planningfunctional safetyformal verificationrtlhvljasperquestachecksverilogsecurityplanninganalysiscoachingschedulestatements of work sowcadence

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