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Senior Post-Si Validation Technical Leader

15.00 to 17.00 Years   Bangalore   26 Oct, 2020
Job LocationBangalore
EducationNot Mentioned
SalaryNot Disclosed
IndustryIT - Software
Functional AreaIT Operations / EDP / MIS
EmploymentTypeFull-time

Job Description

Job ID: JR0147391Job Category: EngineeringPrimary Location: Bangalore, KA INOther Locations:Job Type: Experienced HireSenior Post-Si Validation Technical LeaderJob Description This is a senior technical leadership role in a highly dynamic organization working on industry leading data center SoC products. This role is responsible to drive Post-Si Validation driving validation architecture, drive the teams to develop high quality Post-si test plans/content development and deliver highest quality of coverage meeting the production quality expectations for the SoC. Uses and applies emulation and platform level tools and techniques to ensure functional quality and performance to spec. Responsible for the development of methodologies, execution of validation plans, and debug of complex failures. Requires broad understanding of multiple system areas and requires interfaces with SoC Architecture, Design, and Pre-silicon Validation teams in improving post-silicon test content and design for validation capabilities. Will technically represent validation in various senior management reviews and be accountable for making technical decisions for the team and program. Provides guidance/mentor ship different validation leads/engineers and plays key role in strengthening technical capabilities in the teamQualificationsQualifications: Bachelors/Masters in Hardware Engineering or Electrical/Electronic Engineering or Computer Engineering or Computer Science with 15+ years of experience Candidate must have high degree of Hardware architecture/ microarchitecture experience in CPU/SoC/Chipset/and one of the subsystems areas given below Strong knowledge and skills of Intel IA (IA32 architecture with uArch debug knowledge of Intels Core and Uncore or equivalent architecture.) Deep understanding of Cache coherency, virtualization, system level memory and Power Management architecture knowledge is a must Hands on work in finding bugs in post silicon through fine tuned content in the domain of coherency and concurrency [cross products with PM, PCIe, ethernet etc] Good understanding of memory Controller / DDR (2/3/4) memory architecture and debug Hands-On experience of complex SoC sightings and exposure to running cross-site TFs Knowledge on Debug Tools for JTAG, on chip trace features and ability to debug via OSC/LAs etc; Usage of any Post-Si debug tools (e.g., logic analyzers, oscilloscopes, things like ChipScope on FPGAs, etc.), usage of different Analyzers/exercisers (PCIe etc.) o Familiarity with FW (embedded uC) debug - ARC or Extensa LX-series uC preferredo Knowledge of ARM PM concepts (e.g., P/Q-channel) is a plus Pre-silicon Design / Validation knowledge is a value add. Excellent written and oral communications and experience of working in a cross functional and cross site team environment are essential, combined with ability to handle high level technical ambiguity.Inside this Business GroupThe everyday contributions of the Intel Validation Engineering (iVE) team are essential to retaining/regaining Intels product leadership. We validate, debug, and tune the newest designs and world-changing technologies that enrich the lives of every person on earth. We play a critical role in completing the PRQs of Intel products and in Intels ability to deliver the annual technology platforms in our roadmap.Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.Legal Disclaimer:Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at www.jobs.intel.com and not fall prey to unscrupulous elements.INExperienced HireJR0147391Bangalore,

Keyskills :
javaenvironmentsql serversqlcustomer relationsdata centercache coherencycomputer sciencepower managementsenior managementbehavioral traininghardware engineeringtechnical leadership

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