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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | IT - Software |
| Functional Area | Embedded / System Software,General / Other Software |
| EmploymentType | Full-time |
Job ID: JR0172343Job Category: EngineeringPrimary Location: Bangalore, KA INOther Locations:Job Type: Experienced HireSenior SD Lead/ ManagerJob DescriptionJob Requirement: In this position, you will be responsible for all aspects of Netlist-to-GDSII closure activities of Intels SoCs in lower technology nodes. Your tasks will include but not limited to: Drive and own hands-on design convergence and quality for large blocks, clusters from RTL to GDS [Synthesis, Place and Route, Timing, Physical Verification etc]. Work extensively with implementation and RTL teams to help optimize/converge the designs and drive PPA improvements Drive design methodologies and key functional areas providing technical leadership and guidance Well versed with the Block and Full chip level timing closure (STA) methodologies, ECO generation and predictable convergence. Well versed with parasitic extraction, LVS/DRC and other Physical verification checks Ensure cross teams communications with Logic and Arch Teams and also with Full-Chip Timing, CAD and Integration Teams Influence tools, flows and overall RTL to GDS2 physical design methodology with a data driven approach Drive projects execution planning and manage team technically and org wiseQualificationsQualifications: Education: B.Tech. or M.Tech. in Electrical/Electronics Engineering with 10-15 years of experience Key skills: Experience in physical implementation with multiple design cycles in ASIC flow is required. Experience of leading a team for PnR and timing closure of complex designs. Strong knowledge of synthesis, physical design, STA and verification flows, methodology and knowledge of all aspects of physical design is required. Experience in 10nm or below technologies. Knowledge of low power flow (power gating, multi-Vt flow, power supply management etc.) Experience in industry standard tools such as, Synopsys ICC2/Fusion compiler, Innovus, PrimeTime, ICV, Mentor Calibre, and Calibre DRV is required. Experience in scripting languages, preferably Perl, Python, Tcl, etc.is preferred. Excellent oral and written communication skills. Experience in project/milestone planning, team health/career growth planning of team members, team growth.Inside this Business GroupThe Core and Client Development Group (C2DG) is a worldwide organization focused on the development and integration of SOCs, Core , and critical IPs that power Intels leadership products, driving most of the Client roadmap for CCG, Delivering Server First Cores that enable continued growth for DCG and invest in future disruptive technologies.Legal Disclaimer:Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at www.jobs.intel.com and not fall prey to unscrupulous elements.INExperienced HireJR0172343Bangalore,
Keyskills :
power flowpower supplytiming closurephysical designsupply managementtechnical leadershipparasitic extractionphysical verificationcadgdsrtlstaecopnrppatclips