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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | Telecom / ISP |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
RESPONSIBILITIES:Expertise in handling RTL to GDS2 flowExposure in Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/ IRExtensive Experience in handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache RedhawkHands on experience on 16nm, 14nm, 12nm, and sub-10nm projectsGood knowledge in Physical design, STA, methodology scripts (Tcl), knowledge on Perl, PythonWork in an Individual Contributor roleREQUIREMENTS:5-8 years of professional experience in the semiconductor industryExperience in FinFET & Dual Patterning nodes such as 16/ 14/ 10/ 7nmHigh-frequency design experienceCPU/ GPU/ memory controller/ ddr or other high speed units experienceExcellent physical design and timing backgroundSynopsys tools experience not a must but preferredWould also prefer MNC experienceFamiliarity with all Design areas and tools and solid understanding of design/ technology interactionsGood understanding of computer organization/ architectureStrong analytical/ problem solving skills and pronounced attention to detailsMust be a self-starter, and able to independently drive tasks to completionGood teamwork and communications skills are mandatoryBS + 12 years or MS + 10 years Electrical Engineering and/ or Computer Architecture work experience,