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Job Location | Bangalore |
Education | Not Mentioned |
Salary | Not Disclosed |
Industry | Manufacturing |
Functional Area | General / Other Software |
EmploymentType | Full-time |
At Rambus, we are turning incredible possibilities into everyday reality by helping to deliver the innovations that greatly impact the world we live in. We create leading-edge semiconductor and IP products, spanning memory and interfaces to security to smart sensors. Our products are integrated into tens of billions of devices and systems around the globe, running critical applications for Big Data, Internet of Things ( IoT), mobile, consumer and media platforms. And our history runs deep - we have been in Silicon Valley for 25 years and are continually anticipating key technology trends and are developing innovations that drive market changes. From a pure IP provider to becoming a fabless chipmaker, Rambus is evolving to address critical challenges in the semiconductor industry. As a dynamic organization, we are always seeking to hire exceptional talent to join some of the brightest inventors and engineers in the world to explore their passions to develop products that have real life impact. As well, Rambus benefits are among the most comprehensive and competitive in Silicon Valley. ResponsibilitiesLead complete ownership of IP physical implementation, integration and TC implementation till TO. Take complete ownership for implementation of Testchip Top level and Block level designs Responsible for independent planning and execution of all aspects of physical design including synthesis, floor planning, place and route, Clock Tree Synthesis, Clock Distribution, IP integration, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out on 28nm nodes or below. Must have participated in all stages of the design. ( floor planning, placement, CTS, routing, crosstalk avoidance, physical verification, IREM) Well versed with the level timing closure ( STA), timing closure methodologies. Should be able to provide clear directions to the team on PnR flows. Role involves tasks in estimating power using industry standard tool , designing power grid , analyze power grid, doing static IR drop, dynamic IR drop Role involves analyzing DRC, LVS, ERC and PERC rule files for industry standard layout verification Working on very leading technology nodes: 14nm, 10nm, 7nm. Responsible for integrating the top level IP, and collateral deliverables to the customer. Well aware of place and route methodologies and hands on experience with timing convergence Good communication skill to negotiate with top level for convergence. Work closely with Project leader for creating schedule, tracking and raising issues / risks to project management. Participate in Mentoring new joinees in the group on technical skills. Provide inputs for CAD/ DA team from Design Implementation perspective. Work closely with DFT team on scan aspects and provide inputs from physical design. Continuously work on methodology and productivity improvements. QualificationsMust have minimum Bachelors degree in EE from a reputed institute. Must have atleast 8 - 10 years of experience, out of which atleast 8 years should be related to physical design at chip level / block level. Must have implemented and completed a minimum of 8 design tapeouts. Must have detailed knowledge of EDA tools and flows, Cadence related foundation flows and RTL2GDS flow is desired Experience in Tcl/ Tk, PERL is a Plus Synthesis experience and exposure besides chip implementation flows is an added advantage. Rambus offers an extremely competitive compensation package, which includes a strong base salary, bonus, equity, matching 401( k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program and gym membership.,
Keyskills :
cadence controlling diagnostics fft gsm physicaldesign signalintegrity tatementsofw ksow internetofthings clocktreesynthesis bigdata edatools flo planning timingclosure guidevelopment technology