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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | IT - Hardware / Networking |
| Functional Area | Network / System Administration |
| EmploymentType | Full-time |
SMTS / Principal ASIC Design Engineer - Network Security - Aquantia Corp SMTS / Principal ASIC Design Engineer Network Security Education: Graduate Degree in Electrical / Electronics Engg. (post Graduate is a plus)Experience / Skills:10+ years of ASIC RTL Design experience and Verilog / System Verilog proficiencyExperience with multiple clock and power domainsExtensive experience with MACSEC / IPSEC protocol and security implementationsRTL Design and implementation of MACSEC / IPSEC / AES / SHA / RSA cores for high performance networking applicationCreate block - level micro - architecture specification and that outline interfaces , timing behavior , design tradeoffs , Review vendor IP integration guidelines and verify the compliance throughout the design flowRun integrity check tools such as Lint / CDC / DFT / LEC / UPF to satisfy coding and implementation guidelinesParticipate in design verification process by reviewing test plans , coverage reports , writing assertionsand other design modifications to improve verification qualityParticipate in physical implementation process by providing synthesis constraints , timing exceptions andmaking design updates to meet area , power and performance goalsBe able to work and communicate with multi - site teamsResponsible for the review of netlist releases (pre / post - route / eco , block / chip)ASIC product life cycle experience (requirements , design , implementation , test and post - silicon validation),
Keyskills :
logicvalidationverificationverilogfpgaproductlifecyclertldesignlifecycleasicdesignsystemverilogdesignverificationdftrtllecrsaecocdcaesetwksecurity