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SMTS Product Dev Engn/IP Efuse Macro / Circuit Design and Layout Development Engineer

3.00 to 5.00 Years   Bangalore   25 May, 2020
GLOBALFOUNDRIES
Job LocationBangalore
EducationNot Mentioned
SalaryNot Disclosed
IndustryManufacturing
Functional AreaEmbedded / System SoftwareGeneral / Other Software
EmploymentTypeFull-time

Job Description

*About GLOBAL FOUNDRIESGLOBAL FOUNDRIES is the world s first full-service semiconductor foundry with a truly global footprint. Launched in March 2009, the company has quickly achieved scale as one of the largest foundries in the world, providing a unique combination of advanced technology and manufacturing to more than 250 customers. With operations in Singapore, Germany and the United States, GLOBAL FOUNDRIES is the only foundry that offers the flexibility and security of manufacturing centers spanning three continents. The company s 300mm fabs and 200mm fabs provide the full range of process technologies from mainstream to the leading edge. This global manufacturing footprint is supported by major facilities for research, development and design enablement located near hubs of semiconductor activity in the United States, Europe and Asia. GLOBAL FOUNDRIES is owned by the Mubadala Development Company.Position Title: IP Efuse Macro / Circuit Design and Layout Development EngineerWork Area: Foundry IP DevelopmentLocation : BangaloreSummary of Role :

  • Work with a IP Development team on the circuit design, layout and timing of Efuse Macro Designs in various technology nodes.
Essential Responsibilities :
  • Use industry standard design tools to perform gate/transistor level electrical circuit design and physical layout, circuit design verification / simulation with electrical, physical and timing rules generation for Foundry circuits such as Standard Cell Logic libraries, IO libraries, and Efuse Macros.
, *Required Qualifications :
  • Requires a Bachelor of Science (B.S.) or equivalent degree in a related field from an accredited university.
    • B.S. + minimum of 8 years of relevant experience
    • M.S. + minimum of 7 years of relevant experience
    • PhD + minimum of 5 years of relevant experience
  • Minimum of 3 - 5 years of experience with digital/analog IP circuit design, layout, and timing experience
  • Language Fluency Fluent in English Language written & verbal.
  • Must have transistor level electrical circuit design understanding.
  • Must be able to interpret electrical design specifications
  • Applicant should have a proficient knowledge of and experience with EDA tools for schematic and physical layout, design rule checking (DRC), layout versus schematic checking (LVS, schematic and layout extraction, methodology checking, circuit simulation and analysis, and various physical and electrical rules
  • Knowledge of AIX/NFS, Linux, Shell, Tcl, Perl
  • Must have good technical verbal and written communication skills and ability to work with cross functional teams is necessary
  • Candidates who are self-driven and have worked in a global team environment with a successful track record of on-time high quality IP design creation.
  • Be able to collaborate with program and technical design leads on multiple concurrent projects.
  • Should have excellent problem solving skills, written & oral communication, teaming & inter-personal skills
  • Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs
  • Shows depth in a technical discipline and breadth across disciplines and is recognized within the business unit as an authority in his/her area(s) of specialization.
  • Shows Initiative and creativity resulting in high degree of innovation while showing the capacity to solve major problems of an advanced complexity affecting various departments or businesses.
Additional Eligibility Qualifications:Preferred Qualifications:
  • Should have experience with various types of layout methods for transistor level circuit design
  • Knowledge of the end-to-end IP and Chip design cycles
  • Knowledge in RF technologies (Bulk, CMOS & SOI) process is desired.
  • Project management, Schedule development, SOW creation skills are desired.

Keyskills :
ppap productdevelopment apqp inspection documentation designrulechecking layoutversusschematic edatools chipdesign standardcell circuitdesign designverification esignrulecheckingdrc

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