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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | IT - Software |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
Oversees definition, design, verification, and documentation for SoC (System on a Chip) development. Determines architecture design, logic design, and system simulation. Defines module interfaces/ formats for simulation. Performs Logic design for integration of cell libraries, functional units and sub-systems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Performs all aspects of the SoC design flow from high-level design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing. Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results. May also review vendor capability to support development.BS in Electrical or Computer Engineering with 12 years experience or MS in Electrical or Computer Engineering with 10 years experience in handling end2end execution of complex SoC with focus on Full chip floor-planning as primary responsibility.Excellent verbal and written communication skills.Preferably experience in 7 nm, 10 nm & 14nm flowsPerforming a wide range of back-end activities, including synthesis of RTL, DFT insertion, power optimization Floor-planning, PnR (Place and Route) , Clock Tree Synthesis (CTS) , Timing closure (STA) , DRC, LVS, Antenna checks, IR drop (RedHawk) , multi voltage checks etc.Participating in the development of a back-end ASIC design flow.Expertise in Synopsys suite (IC Compiler, Primetime, Design Compiler) .Experience of UPF low power design through synthesis, place and route.,
Keyskills :
high level designclock tree synthesis asic designdesign flow logic designlevel design music makingfloor planning