SOC RTL Design Engineer

5.00 to 10.00 Years Bangalore 17 Sep, 2020

Job Location	Bangalore
Education	Not Mentioned
Salary	Not Disclosed
Industry	IT - Software
Functional Area	General / Other Software
EmploymentType	Full-time

Job Description

Minimum qualifications

Strong fundamentals in digital ASIC design; experience using Verilog or VHDL
Experience with ASIC design/micro-architecture, synthesis, timing/power analysis

Preferred qualifications

Knowledge of SOC architecture
Familiarity with high performance and low power design techniques
Some hands-on experience in design verification and/or physical design
Knowledge of FPGA and emulation platforms
Knowledge of assertion-based formal verification
Domain knowledge in one or more of these areas: fabric, memory controller, security, caches, coherence, MMU, high speed interfaces/protocols

Roles and Responsibilities

Work with chip architect to understand architecture concept and high level requirements
Conceive of the micro-architecture and write design specifications
Convert design spec to Verilog RTL
Provide assertions for the design to ensure RTL is of the highest quality
Support the verification team to devise appropriate test plans and verification strategy
Collaborate with physical design team to close timing, area targets, reliability, etc.
Collaborate with power team on power analysis and closure
Assist in emulation, FPGA, prototyping efforts
Assist in silicon bring-up, debug and characterization

Keyskills :
verilogfpgaxilinx isehdlaltera quartusrtl designasic designpower analysisphysical designformal verificationdesign verificationdesign specificationssocrtlmmuvhdldesigntimingclosureasic

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SOC RTL Design Engineer

Job Description

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