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SoC STA/Full chip Timing Technical Lead

10.00 to 11.00 Years   Bangalore   15 Oct, 2020
Intel Technology India Pvt Ltd
Job LocationBangalore
EducationNot Mentioned
SalaryNot Disclosed
IndustryIT - Software
Functional AreaGeneral / Other Software,Web / Mobile Technologies
EmploymentTypeFull-time

Job Description

Job ID: JR0143144Job Category: EngineeringPrimary Location: Bangalore, KA INOther Locations:Job Type: Experienced HireSoC STA/Full chip Timing Technical LeadJob DescriptionIn this role as SoC fullchip Timing Lead you will be part of Server team chartered with delivering high performance SoCs. This is a technical leadership role directly responsible for all aspects of SoC timing closure working closely with design and implementation team. The additional key responsibilities include

  • Responsible for performing block level and full chip level hierarchical timing analysis for complex multi-million Server and AI SOC.
  • Responsible for generating and verifying block level and full chip level implementation/Sign-off timing constraints for functional modes and other modes like DFT.
  • Responsible for working closely with the physical design team to generate clock balancing guidelines and timing fixes considering all modes all corners and sign-off the design for Tape-out.
  • Qualifications:
  • Expertise and in-depth knowledge of industry standard EDA tools (Prime time, GCA), as well as proficiency in scripting languages, such as, Python, Perl, and Tcl.
  • Knowledge of circuits, SPICE simulations, and/or transistor level STA.
  • Demonstrate a deep understanding of Static Timing Analysis, timing constraints generation and management, and timing convergence.
  • Capable of analyzing and converging cross-talk delay, noise glitch, process variation, and electrical/manufacturing rules and the modeling of these effects in deep-sub micron processes required.
  • Experience in generating, handling and validating timing/SI models to reduce the memory footprint and Sign-off run times and simultaneously ensuring required accuracy at various stages of design cycle
  • Demonstrated capability of leading silicon architecture and hands-on skills in RTL/Logic design for timing closure desired.
  • Knowledge in physical design and optimization e.g. placement, routing, cell sizing, buffering, logic restructuring, etc. to improve timing and power, and implementing them through ECOs.
  • Experience in 7 nm, 10 nm & 14nm Implementation flows is highly desired
  • CPU implementation background would be a plus.
  • An excellent team player and ability to work with different teams smoothly to achieve common goals and solid communication skills is a must
  • Capable of managing ambiguity and get to technical decisions quickly working with stake holders and also provide clear and crisp updates to Senior Management.
Qualifications
  • BS in Electrical or Computer Engineering with 12+ years experience or MS in Electrical or Computer Engineering with 10+ years experience in Synthesis, Timing methodologies and flow development.
Inside this Business GroupThe Silicon Engineering Group is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs that power Intel s leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.Legal Disclaimer:Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at www.jobs.intel.com and not fall prey to unscrupulous elements.INExperienced HireJR0143144Bangalore,

Keyskills :
javasql serversqlcustomer relationsstatic timing analysiseda toolsphysical designtiming analysistechnical leadershipoptimization strategiesedasocperlips

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