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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | IT - Software |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
Job ID: JR0150087Job Category: EngineeringPrimary Location: Bangalore, KA INOther Locations:Job Type:SOC STA/Timing Sign-off EngineerJob DescriptionJob DescriptionXeon Server Solution (XSS) group in Intel is responsible for delivering complex Servers SoC catering to high bandwidth memory requirements for Data-center & cloud applications.Main Duties and Responsibilities:We are looking for enthusiastic, motivated and self-driven engineer in area of Static Timing Analysis who can take care of below responsibilities:Responsible for performing block level and full chip level hierarchical timing analysis for complex multi-million Server and AI SOC.Responsible for generating and verifying block level and full chip level implementation/Sign-off timing constraints for functional modes and other modes like DFT.Responsible for working closely with the physical design team to generate clock balancing guidelines and timing fixes considering all modes all corners and sign-off the design for Tape-out.QualificationsBS in Electrical or Computer Engineering with 15+ years experience or MS in Electrical or Computer Engineering with 12+ years experience in Synthesis, Timing methodologies and flow development.Expertise and in-depth knowledge of industry standard EDA tools (Prime time, GCA), as well as proficiency in scripting languages, such as, Python, Perl, and Tcl.Knowledge of circuits, SPICE simulations, and/or transistor level STA. Demonstrate a deep understanding of Static Timing Analysis, timing constraints generation and management, and timing convergence. You are capable of analyzing and converging cross-talk delay, noise glitch, process variation, and electrical/manufacturing rules and the modeling of these effects in deep-sub micron processes required.Experience in generating, handling and validating timing/SI models to reduce the memory footprint and Sign-off run times and simultaneously ensuring required accuracy at various stages of design cycleYou have demonstrated a capability of driving hardware architecture and hands-on skills in RTL/Logic design for timing closure desired.Knowledge in physical design and optimization e.g. placement, routing, cell sizing, buffering, logic restructuring, etc. to improve timing and power, and implementing them through ECOs.Preferably experience in 7 nm, 10 nm & 14nm Implementation flowsCPU implementation background would be a plus.Excellent verbal and written communication skills.QualificationsBS in Electrical or Computer Engineering with 15+ years experience or MS in Electrical or Computer Engineering with 12+ years experience in Synthesis, Timing methodologies and flow development.Inside this Business GroupThe Silicon Engineering Group is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs that power Intel s leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.INJR0150087Bangalore,
Keyskills :
static timing analysiseda toolsmusic makingtiming closurephysical designtiming analysiscommercial modelswritten communicationhardware architectureoptimization strategie