| Hyderabad Jobs |
| Banglore Jobs |
| Chennai Jobs |
| Delhi Jobs |
| Ahmedabad Jobs |
| Mumbai Jobs |
| Pune Jobs |
| Vijayawada Jobs |
| Gurgaon Jobs |
| Noida Jobs |
| Hyderabad Jobs |
| Banglore Jobs |
| Chennai Jobs |
| Delhi Jobs |
| Ahmedabad Jobs |
| Mumbai Jobs |
| Pune Jobs |
| Vijayawada Jobs |
| Gurgaon Jobs |
| Noida Jobs |
| Oil & Gas Jobs |
| Banking Jobs |
| Construction Jobs |
| Top Management Jobs |
| IT - Software Jobs |
| Medical Healthcare Jobs |
| Purchase / Logistics Jobs |
| Sales |
| Ajax Jobs |
| Designing Jobs |
| ASP .NET Jobs |
| Java Jobs |
| MySQL Jobs |
| Sap hr Jobs |
| Software Testing Jobs |
| Html Jobs |
| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | IT - Software |
| Functional Area | Embedded / System Software,General / Other Software |
| EmploymentType | Full-time |
Job ID: JR0150951Job Category: EngineeringPrimary Location: Bangalore, KA INOther Locations:Job Type: Experienced HireSOC STA/Timing Sign-off EngineerJob DescriptionXeon Server Solution (XSS) group in Intel is responsible for delivering complex Servers SoC catering to high bandwidth memory requirements for Data-center & cloud applications.Main Duties and Responsibilities: We are looking for enthusiastic, motivated and self-driven engineer in area of Static Timing Analysis who can take care of below responsibilities:Responsible for performing block level and full chip level hierarchical timing analysis for complex multi-million Server and AI SOC. Responsible for generating and verifying block level and full chip level implementation/Sign-off timing constraints for functional modes and other modes like DFT. Responsible for working closely with the physical design team to generate clock balancing guidelines and timing fixes considering all modes all corners and sign-off the design for Tape-out.QualificationsBS in Electrical or Computer Engineering with 15+ years experience or MS in Electrical or Computer Engineering with 12+ years experience in Synthesis, Timing methodologies and flow development. Expertise and in-depth knowledge of industry standard EDA tools (Prime time, GCA), as well as proficiency in scripting languages, such as, Python, Perl, and Tcl.Knowledge of circuits, SPICE simulations, and/or transistor level STA. Demonstrate a deep understanding of Static Timing Analysis, timing constraints generation and management, and timing convergence. You are capable of analyzing and converging cross-talk delay, noise glitch, process variation, and electrical/manufacturing rules and the modeling of these effects in deep-sub micron processes required. Experience in generating, handling and validating timing/SI models to reduce the memory footprint and Sign-off run times and simultaneously ensuring required accuracy at various stages of design cycleYou have demonstrated a capability of driving hardware architecture and hands-on skills in RTL/Logic design for timing closure desired. Knowledge in physical design and optimization e.g. placement, routing, cell sizing, buffering, logic restructuring, etc. to improve timing and power, and implementing them through ECOs.Preferably experience in 7 nm, 10 nm & 14nm Implementation flowsCPU implementation background would be a plus.Excellent verbal and written communication skills.Inside this Business GroupXeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOCs and critical IPs sustain Intels Xeon and 5G networking roadmap.Legal Disclaimer:Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at www.jobs.intel.com and not fall prey to unscrupulous elements.INExperienced HireJR0150951Bangalore,
Keyskills :
static timing analysiseda toolstiming closurephysical designtiming analysiscommercial modelsbehavioral trainingwritten communicationhardware architectureoptimization strategiesedasocperl