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STA/Signoff Methodology-Implementation Lead

10.00 to 12.00 Years   Bangalore   10 May, 2021
Intel Technology India Pvt Ltd
Job LocationBangalore
EducationNot Mentioned
SalaryNot Disclosed
IndustryIT - Software
Functional AreaGeneral / Other Software
EmploymentTypeFull-time

Job Description

Job ID: JR0161243Job Category: EngineeringPrimary Location: Bangalore, KA INOther Locations:Job Type:STA/Signoff Methodology-Implementation LeadJob DescriptionIn a fast-paced, leading-edge environment with endless possibilities of innovating and learning, you will be responsible for leading and defining signoff design methodologies of complex and world class Graphics, Media and Display IPs. In this position, your responsibilities may include, but not be limited to:

  • Defining and implementing signoff methodology for all areas related to Performance Verification (PV) including timing analysis, power estimation, Circuit Quality, Extraction and noise glitch analysis across internal and external foundry processes
  • Developing robust ASIC design and verification methodology to meet PV requirements including PVT corner definition for design convergence, clock uncertainty requirements, timing budgeting, repeater planning, automatic constraints/exceptions generation & management, and other key differentiating capabilities for quality & efficient timing closure
  • Working closely with process technology team to understand process characteristics and setting appropriate design constraints to model on-chip variation effects, power-supply variation, process aging and other PV/Si miscorrelation effects in timing analysis flows.
  • Engaging closely with Design teams to understand the design & convergence challenges and derive methods to provide recipes with a focus on PPA & TAT optimizations.
  • Developing timing flows, understand design requirements/objectives and develop signoff conditions and milestone checklists appropriate with the design project goals. Work with 3rd party EDA vendors to resolve issues and drive improvements in design convergence and signoff
The ideal candidate should exhibit behavioral traits that indicate:
  • Self-motivator with strong problem-solving skills
  • Strong leadership skills with ability to mentor junior designers
  • Excellent interpersonal skills, including written and verbal communication
  • Ability to work as part of a team and collaborate in a high-paced atmosphere
  • Ability to provide technical direction to the team and influence project execution and methodology
Qualifications
  • Mtech/Btech Engineering Degree in field of Electrical, Electronics, Computer Science with 8+/10+ yrs of relevant RTL2GDS experience
  • Demonstrated ability in methodology development in areas of Timing analysis, timing convergence, SI/Noise analysis, Signoff quality (PVT, process variation effects, guardbanding, etc), Timing ECOs, PV/Noise modelling, .libs, is a must
  • Expertise and in-depth knowledge of industry standard EDA tools (Timing, Synthesis, P&R) and ASIC design flow is required
  • Multi-voltage scenarios design handling knowledge is expected. STA closure/convergence execution with Low power design closure is an added advantage
  • Proficiency in scripting language, such as, Perl & Tcl required
Inside this Business GroupINJR0161243Bangalore,

Keyskills :
deliverymanagementslaaspcommissioningeda toolsasic designdesign flowproblem solvingtiming analysiscomputer sciencepower estimationproject executionleadership skillstechnical direction

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