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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Rs 28 - 40 Lakh/Yr |
| Industry | IT - Software |
| Functional Area | Embedded, VLSI,Hardware / Telecom Equipment Design |
| EmploymentType | Full-time |
Standard Cell Design EngineersExp: 8 15 yrsLocation: Bangalore- As part of this team, you are responsible for standard cell library content definition, circuit implementation, leading the standard cell pathfinding activities with active collaboration with process technologists, product design stake holders, and EDA vendors to achieve best-in-class cell/block level PPA. You will also be responsible for leading the standard cell benchmarking and competitive analysis activities and driving technology enhancements for FIP leadership.- Supporting test-chip planning and Si validation of std cells to track yield, Vmin and power/performance, the design of chip layout circuit design, circuit checking, device evaluation and characterization, documentation of specifications, modification and evaluation of semiconductor devices and components, performing developmental and/or test work, reviewing product requirements and logic diagrams, planning and organizing design projects or phases of design projects are additional responsibilities. - Responds to customer/client requests or events as they occur. - Develops solutions to problems utilizing formal education and judgement.Qualifications:You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: - One must possess Master degree(M.E/M.Tech) with VLSI specialization. A minimum of 8+ years of relevant experience in standard cell layout design, silicon implementation, and/or process technology. Additional/Desired Qualifications: - Experience in digital circuit design, including CMOS combinatorial logic and sequential element design and layout. - Experience using industry-standard design automation tools for one or more of the following areas: circuit - simulation, cell characterization, synthesis, place and route, physical design verification and reliability verification. - Experience in scripting (TCL, Perl) for design automation - Experience working in the Linux environment and its development tools - Experience in EDA tool/flow/methodology, product and IP developments are strongly preferred.
Keyskills :
clock tree synthesisroutecmossynthesisstandard cell layoutdigital circuits designcell characterizationplace