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Job Location | Bangalore |
Education | Not Mentioned |
Salary | Not Disclosed |
Industry | IT - Software |
Functional Area | General / Other Software |
EmploymentType | Full-time |
Given architecture, create WBS and effort estimates. Get the designs implemented and/ or executed. Complete project ownership from concept to delivery. This includes identifying risks, dependencies, creating mitigation plan, tracking project schedule and take corrective action as maybe required. Create module level details from architecture, coding, simulation and perform peer reviews. Apply the methodologies for design, verification or validation. Define, create and maintain all project related documentation. Supervise and Mentor at- least 2 to 3 senior design engineers. Act as PL in absence of supervisor. Organize and manage conference calls, discussion with customers and resolve issues. Create proposal for new project enquiries. Key Skill Sets: Proficient in VLOG. VHDL knowledge is preferable. Knowledge of C and scripting using Perl, TCL/ Tk. Proficient in FPGAs tools. Proficient in Synthesis, PAR and Timing closure Proficient in simulation tools like Modelsim, Questasim. Proficient knowledge of different memory and interface devices. Ability to perform peer reviews. Create project plan using MS Project. Soft skills Xilinx FPGA/ tools knowledge is preferred. Video knowledge is preferable. Personality Attributes: Good Communication and Documentation skills Responsible, reliable, accessible, and responsive. Strong analytical and problem- solving skills. Agile, proactive, knows how to work with ambiguous specifications,
Keyskills :
environmental impact assessmentsoft skillstiming closurewbsperlvhdlagilevideodesignxilinxtimingclosureschedulemodelsimscriptingsynthesisownershipanalyticalrective action