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Urgently hiring For Principal Verification Engineer

10.00 to 16.00 Years   Bangalore   16 Mar, 2020
ACZ Global Pvt Ltd
Job LocationBangalore
EducationNot Mentioned
SalaryNot Disclosed
IndustryRecruitment Services
Functional AreaGeneral / Other Software
EmploymentTypeFull-time

Job Description

Dear Candidate, We have a exciting opportunity for a SVE with a semiconductor based industry. Required Skills

  • 10+years, equivalent experience in ASIC design and verification.
  • Familiar with System Verilog Assertions, Code and Functional Coverage and Formal verification techniques.
  • Experience in verifying designs at system level and block level using constrained random verification.
  • Expert in System Verilog and OVM/UVM based verification.
  • Strong experience in ASIC design verification flows and DV methodologies.
  • Expert in coding SV Testbench, drivers, monitors, scoreboards, checkers
  • Highly motivated and be able to work both independently and as a member of team.
  • Strong and independent design debugging capability.
  • Strong programming and scripting language capability.
  • Expert in using verification tools like VCS, IUS, modelsim, Debussy etc
Please share your updated resume with Total EXP: Rel Exp: Current CTC: Expected CTC: Notice Period: Please call directly for quick processing of your CV share your updated CV to below mail id; Regards, Harshitha +91 6366363111 harshitha@aczglobal.com ,

Keyskills :
verificationuvm designfailure analysis asic design system verilogformal verification

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