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VLSI Digital STA Synthesis Timing Architect

8.00 to 10.00 Years   Bangalore   02 May, 2019
Wipro Limited
Job LocationBangalore
EducationNot Mentioned
SalaryNot Disclosed
IndustryIT - Software
Functional AreaGeneral / Other Software
EmploymentTypeFull-time

Job Description

Key skills required for the job are:

  • Analog Circuit design-L3 (Mandatory)
Minimum work experience:5 - 8 YearsVLSI AnalogCircuit Design EngineerNumber ofpositions: 1Location:Bangalore (may need to travel onsite to Europe)Experiencein analog and mixed signal CMOS IC Design.Experiencein: high precision oscillators, ADC, DAC, Linear analog amplifiers, RC-filters,PLL.Experiencewith basic RF and DCXO will be plus.Knowledgeof basic building blocks of analog sub systems.Analogcircuit design experience in lower technology nodes like TSMC 16nm/7nm.Shouldpossess good knowledge on CMOS functionality and fabrication process, andchallenges in latest technology nodes.Should haveexperience in circuit simulation analysis (DC, TRAN, HB, PSS, Ageing, MonteCarlo)Tools Skill:Wellexperienced in using industry standard EDA tools like Cadence Virtuoso,Specter, APS, XPS etc.Knowledgeof UNIX, shell scripting, Cadence Design Environment, Roles & Responsibilities:Minimum Experience Required: 8-10 YEARS Mandatory Skills: VLSI Physical Design Planning Static Timing analysis, Hardware Designing, ASIC Design, ASIC Synthesis Desirable Skills: VLSI Physical Design Packaging, Place and Route - IC Compiler Language Skills: English Language

Keyskills :
photoshopstatic timing analysis

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