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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | IT - Software |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
DFT synthesis Good knowledge of Hierarchical scan synthesis with : o Scan segmentations o Test models Handle module level scan insertion. Handle device scan insertion with multiple clock domains. ATPG Able to do Block/ Device level pattern generation and simulations. Scan interleaved with memory bist patterns gen and validation. Device level transition delay testing with multiple clocks, handling exceptions. Able to do Sequential ATPG with RAMs and latches, coverage analysis. Path Delay tests, delay coverage analysis. Excellent knowledge on usage of ATPG tool.- Able to do Silicon debug and diagnostics Delay tests using PLL, silicon debug and diagnostics. BIST Good knowledge of On-chip scans compression or bist techniques and test time reduction. Memory BIST integration in SoC and verification, selecting the optimal mem., Roles & Responsibilities:Mandatory Skills: VLSI Design For Testability - DFT Static Timing analysis, VLSI Built In Self Test - BIST, VLSI Memory BIST and Boundary SCAN, VLSI Design For Testability - DFT, Boundary and Scan synthesis, ATPG - VLSI Automatic Test Pattern Generation Desirable Skills:Language Skills: English Language
Keyskills :
diagnosticsstatic timing analysis verificationtiming analysis testing