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ENGR PRIN, DIGITAL_TL

10.00 to 12.00 Years   Chennai   20 Oct, 2021
ON Semiconductor Technology India Private Limited
Job LocationChennai
EducationNot Mentioned
SalaryNot Disclosed
IndustryConsumer Durables / Electronics
Functional AreaGeneral / Other Software
EmploymentTypeFull-time

Job Description

*Principal ASIC Design EngineerJob DescriptionDesign and develop WIFI MAC/Baseband SOC. The candidate must have strong knowledge of Wireless MAC, SOC and Networking ASIC design. Ideal candidate must have strong background in Hardware Datapath acceleration for Security, Ethernet 802.3 protocol, and Wireless 802.11 ax/ac protocol. Desired Skills and Qualifications

  • Minimum BS degree in EE Engineering and 10-12 years of experience. Preferably an MS in Electrical Engineering or computer Engineering.
  • Experience in the micro-architecture and RTL coding of SOC , Security and Wireless MAC (802.11ax/ac) protocol.
  • Knowledge of 802.11a/b/g/n/ac/ax protocols, Ethernet 802.3 protocols and Security standards.
  • Experience in AXI and AHB interconnect fabrics, DMA, DDR controllers, high-speed peripherals (PCIe, SATA, USB), CPU/Cache, MMU/SMMU.
  • Advanced knowledge of ASIC Design with keen understanding on Performance/Area/Power trade-off.
  • Experience in ASIC implementation methodology steps like lint, CDC, Synthesis, formal verification, and STA.
  • Proficient in Verilog and System Verilog for RTL design or verification.
  • Experience of post silicon bring-up and debug is a plus.
  • Excellent communication skills both written and verbal.
  • Excellent collaboration skills.
, *Responsibilities
  • Micro-architecture and RTL implementation of WIFI SOC modules from spec.
  • Deliver RTL and detailed documentation to verification team, work with verification team on test plan and test coverage.
  • Responsible for ASIC implementation of blocks which include lint, CDC, Synthesis, Timing constraints, formal verification, and STA.
  • Interface with architecture, software, systems, and verification engineers during chip development stage and bring-up.
  • Setup PTPX flow, generate estimated power numbers, analyze results, and work with design team to assist targeting blocks for further power reduction
  • Run Synthesis and ensure design meets timing requirements

Keyskills :
rtl designrtl codingasic designsystem verilogformal verificationcommunication skillselectrical engineeringimplementation methodologymacsocrtlddrdmacdcaxiahbwifisatalintasic

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