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Job Location | Chennai |
Education | Not Mentioned |
Salary | Not Disclosed |
Industry | Consumer Durables / Electronics |
Functional Area | Sales / BD |
EmploymentType | Full-time |
The candidate will be responsible for synthesis/ formal verification and design support for next- generation SoCs subsystems for WIFI/ Connectivity chips. This role will require the candidate to understand and drive Synthesis, Formal verification, and partner with DFT and PD teams for timing convergence. Synthesis of a subsystem/ SOC with multiple Hard Macros FV with LEC in multiple stages of RTL to NL flow.,
Keyskills :
java customerrelations linux automation dft soc rtl lec design macros timing synthesis connectivity ModelChecking AssertionBasedVerification esignsupp malverification The emProving EquivalenceCheckin