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Lead RTL Design Engineer

Fresher   Chennai, Tamil Nadu   07 Nov, 2025
ACL Digital
Job LocationChennai, Tamil Nadu
EducationNot Mentioned
SalaryNot Disclosed
IndustryEngineering / Construction
Functional AreaNot Mentioned
EmploymentTypeFull-time

Job Description

    Role Overview:You should have 6 to 9 years of experience in Synthesis, Constraints, and interface timing challenges. It is preferable to have good knowledge of Power. Your role will require strong domain knowledge in RTL Design, implementation, and Timing analysis. You should be experienced in RTL coding using Verilog/VHDL/System Verilog and have experience in micro-architecture & designing cores and ASICs. Additionally, you should be familiar with Synthesis, Formal Verification, Linting, CDC, Low Power, UPFs, etc. Exposure in scripting (Pearl/Python/TCL) is expected, and you should have strong debugging capabilities in Synthesis, timing analysis & implementation. Collaboration with cross-functional teams to research, design, and implement performance, constraints, and power management strategy for the product roadmap is a key aspect of this role. Being a good team player is essential as you will need to interact with other teams/verification engineers proactively. Your ability to debug and solve issues independently will be crucial in this position.Key Responsibilities:- 6 to 9 years of experience in Synthesis, Constraints, and interface timing challenges- Strong domain knowledge in RTL Design, implementation, and Timing analysis- Experience in RTL coding using Verilog/VHDL/System Verilog- Experience in micro-architecture & designing cores and ASICs- Familiarity with Synthesis, Formal Verification, Linting, CDC, Low Power, UPFs, etc.- Exposure in scripting (Pearl/Python/TCL)- Strong debugging capabilities in Synthesis, timing analysis & implementation- Collaborate closely with cross-function team to research, design and implement performance, constraints, and power management strategy for the product roadmap- Good team player, need to interact with other teams/verification engineers proactively- Ability to debug and solve issues independentlyQualifications Required:- 6 to 9 years of experience in RTL design- Strong knowledge of Power is preferable- Experience in micro-architecture & designing cores and ASICs- Familiarity with scripting (Pearl/Python/TCL)- Strong debugging capabilities in Synthesis, timing analysis & implementation,

Keyskills :
SynthesisRTL DesignVerilogVHDLSystem VerilogMicroarchitectureASIC DesignScriptingDebuggingPower Management

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