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| Job Location | Chennai |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | IT - Software |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
RTL and ASIC development Detailed module design, performance analysis and detailed design specification creation Participate in the RTL implementation, synthesis, formality check as well as ECOs Support post-layout timing closure and verification Participate in the investigation assessment of emerging SerDes/Transceiver technologies IPs Improve Data Command processing bandwidth, reduce latencies increase reliability Support porting the design inttest chips and emulation platforms Support pre-tapeout verification and post-tapeout validation/characterization of the system designed Work closely with FPGA support software and FW engineers tresolve hardware issues and customer issues PHY Development Integrate SERDES PMA and PCS Channels inta final design, including resets, clock domain crossing, power-down controls, calibration logic, and associated register maps. Develop SPI and JTAG interfaces intPLL and PMA/PCS components Develop Block Level Constraints and run synthesis Perform Test Chip Level Constraints and fun synthesis Perform Static Timing Analysis of the PCS. PLL control and full Test Chip blocks and review post- layout timing. Support Verification and Validation groups in testing of SERDES PMA and PCS. Design, simulate, and test data encoder/decoders used in SERDES-based designs 8B/10B and similar encoders/decoders 64B/66B, 128B/130B and similar encoders/decoder Data Scramblers and other high speed datapath logic FEC encoders/decoders and associated test logic. Integrate and simulate SERDES-based designs including Developing external interfaces tother parts of the system and/or FPGA fabric Implementing various control/status functions with associated register maps Developing and Integrating AC/DC JTAG control interfaces Develop and/or integrate tindustry standard SerDes based protocol logic PCIe, Ethernet, MIPI, SDI, Interlaken, CEI, OTN, CPRI, PON, DisplayPort, HDMI, CoaxXpress, JESD204, USB, RapidIO, Fibre Channel, Optical Modules I/F, etc. SerDes support logic such as power reduction algorithms, OOB signaling, CTLE and DFE calibration, etc. Support RTL design engineers with less experience for the functions shown above,
Keyskills :
static timing analysisverification validationtest data rtl designdetail design module designfibre channel