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| Job Location | Delhi |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | Education / Training |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
Details Job Description Responsible for feature list development and development of verification plan. Able to individually contribute to the development of testbench and testcase development. Responsible for writing required documentation on testbenches and/ or testplans. Responsible for debugging the design and follow ups till resolution. Education/ Industry Experience BE/ BTech/ MS/ MSc/ MTech/ ME: Electrical, Electronics, VLSI or Computer Science. Expected experience is about 2-5 years in the relevant area. Skills: Associated with Verification especially using industry standard protocols methodology Can be IP/ ASIC or SoC verification Can be Verification IP Development Desirable experience: Any two of the following protocols: USB, PCI Express, SATA, AMBA Languages: Hands on experience with System Verilog, UVM Verilog at a minimum. Experience with Emulation and prototyping will be an added advantage Location: Delhi/ NCR, Bengaluru, Hyderabad, Bhubaneswar Apply,
Keyskills :
verification uvm design failureanalysis ip systemverilog computerscience socverification soc usb vlsi sata amba writing verilog express science debugging ci asic