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Job Location | Delhi |
Education | Not Mentioned |
Salary | Not Disclosed |
Industry | IT - Software |
Functional Area | General / Other Software |
EmploymentType | Full-time |
Verification Engineer (3 5 years) Skills: UVM / OVM , Verilog Job Locations: Delhi / NCR Total vacancies: 3 Must have experience i.Verification Engineer (3 5 years) | Skills: Must have experience in developing Verification environment from scratchMust be good in Verilog codingMust have Simulators experience usingvcs / ncsim / modelsimKnowledge of UVM / VMM methodology is desirable,
Keyskills :
verificationuvm designfailure analysis ovm vmmncsim verilogOpen Verification Methodo