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Lead Engineer FPGA Verification

8.00 to 10.00 Years   Gurugram   10 Dec, 2019
Ciena India
Job LocationGurugram
EducationNot Mentioned
SalaryNot Disclosed
IndustryIT - Hardware / Networking
Functional AreaGeneral / Other Software
EmploymentTypeFull-time

Job Description

The successful candidate will lead the chip level verification activities for a variety of FPGA designs and will be responsible for (but not limited to) the following:- Establish verification methodology, architecture, and infrastructure including models, generators, monitors, scoreboards, etc.- Work with the design team to establish test priorities and coverage targets.- Create verification plans- Create and executing testcases- Triage regressions, providing reports to the team and driving bug fix activities- Collaborate with peers and mentor junior verification engineers on verification methodologies and best practices for achieving first pass success for FPGAs / IP blocks being used in design.- Provide accurate and timely project schedule estimates.Skills:- Experience in developing testbench environments using System Verilog and UVM.- Experience with both directed and constrained-random stimulus generation and testcase writing.- Good problem solving and debugging skills.- Good sense of overall priorities and ability to make smart trade-offs given the typical timelines of FPGA designs.- Experience with one of Cadence Xcelium simulation tools, Mentor Graphics Questa or Synopsys VCS verification tools.-Basic understanding of Formal verification tools, linting, CDC tools, assertions, functional coverage with covergroups, simulation acceleration and other key verification methodologies.-Working knowledge of protocol BFMs or VIPs for Ethernet / IP, PCIe blocks, AXI etc. Knowledge of IEEE 802.3, Metro Ethernet forum standards, CPRI/eCPRI , ITU-T shall be added plus.-FPGA verification with embedded processors such as RISC-V, ARM or Altera/Intel NIOS processor shall be useful.-Translation of verification testcases towards lab validation with scripts such as PERL/Python- Working knowledge of PC and Unix/Linux operating systems.General ActivitiesCapability to give technical leadership to small team of Verification engineers (mentorship)Independent self-starterStrong commitment to product excellenceExcellent communications skillsCollaboration with stakeholders

  • Strong software analysis, design, coding, testing, and documentation skills.
  • Ability to resolve complex issues that may require design trade-offs.
Areas of impact
  • Position requires proficient troubleshooting and problem solving skills.
  • Team oriented; strong inter-personal skills and ability to understand customers needs, expectations and perspective.
  • Demonstrated ability to multitask on multiple projects.
  • Demonstrated communications skills, both verbal and written, to effectively. communicate/collaborate with remote Quality assurance (QA) and Development teams.
  • Strong commitment to product excellence and quality.
  • Contributes (may take lead role) on a project team of engineers involved in the release and test of software. Quickly comes up to speed in understanding of advanced concepts/methodology and contributes to improving and extending the impact and effectiveness of those concepts or new approaches to the current project.
Experience- Bachelors degree in Engineering or equivalent.- Minimum 8 year experience as an FPGA/ASIC Verification Engineer.*LI-CNRewarding experience. Meaningful outcomes.Making a difference in peoples lives through design and implementation of leading network technologies. Thats what motivates us.A distinct way to workFree thinking, free discussion, and collaboration are the norm. Expect more satisfying outcomes - both personal and professional.Ciena values the diversity of our workforce and respects its employees as individuals, regardless of race, nationality, religion, sexual orientation, gender or age.Ciena is also committed to developing inclusive, barrier-free selection processes and work environments. If contacted in relation to a job opportunity, you should advise Ciena in a timely fashion of the specific needs / accommodation measures which must be taken to enable you to be assessed in a fair and equitable manner. Information received relating to any specific needs / accommodation measures will be addressed confidentially.What you can expect from us
  • You will receive notification of your successful application
  • Successful applicants will be contacted by Talent Acquisition for an initial discussion
  • If suitable you will be considered for the short list and our formal interview process
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Keyskills :
java linux ystemverilog softwareanalysis problemsolving

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