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Lead Engineer Signal Integrity

8.00 to 10.00 Years   Gurugram   10 Dec, 2019
Ciena India
Job LocationGurugram
EducationNot Mentioned
SalaryNot Disclosed
IndustryIT - Hardware / Networking
Functional AreaIT Operations / EDP / MIS
EmploymentTypeFull-time

Job Description

Perform board level SI simulations for new hardware designs. Work with HW design engineers to determine board routing strategy by modeling and simulation of transmission line channels to meet defined channel standards. Define routing constraints and PCB design for board-level EMC mitigation. Provide guidance to the mechanical engineering team on system chassis design to ensure conformity with EMC directives. Recommend proper SI test equipment and test strategies. Review test results and correlate to simulations.Experience

  • Excellent written and spoken communications skills to communicate accurate, organized and detailed test reports and test results.
  • Independent, self-driven, organized and detailed-oriented.
  • Expertise with test equipment such as oscilloscopes, TDR, VNA, spectrum analyzers. Experience with proper probing techniques a must.
  • Knowledge of SERDES technology and tuning techniques.
  • Familiarity with IEEE 802.3 electrical and optical interface standards.
  • Strong knowledge of EMC mitigation strategies at board and system level
  • Ability to read schematics and understand component datasheets.
  • Able to perform SI simulation.
  • Understanding of PCB design and the ability to select appropriate PCB material, define stack-up and routing strategy.
  • B.E./M.Tech in Electronics Engineering
  • Minimum 8+ years hardware engineering experience
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Keyskills :
linux java estequipment customerrelations

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