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| Job Location | Gurugram |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | IT - Hardware / Networking |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
What will you do at Ciena Responsibilities:This position is for an experienced FPGA verification engineer for supporting FPGA development Programs for Packet Networking hardware acceleration of Ethernet, MPLS, and IP OAM and SAT (Service Activation Testing) protocols, statistics, packet timing, TDM circuit emulation, as well as, system glue logic for packet access switching and routing platforms.The successful candidate will lead the chip level verification activities for a variety of FPGA designs and will be responsible for (but not limited to) the following:- Establish verification methodology, architecture, and infrastructure including models, generators, monitors, scoreboards, etc.- Work with the design team to establish test priorities and coverage targets.- Create verification plans- Create and executing testcases- Triage regressions, providing reports to the team and driving bug fix activities- Collaborate with peers and mentor junior verification engineers on verification methodologies and best practices for achieving first pass success for FPGAs / IP blocks being used in design.- Provide accurate and timely project schedule estimates.Skills:- Experience in developing testbench environments using System Verilog and UVM.- Experience with both directed and constrained-random stimulus generation and testcase writing.- Good problem solving and debugging skills.- Good sense of overall priorities and ability to make smart trade-offs given the typical timelines of FPGA designs.- Experience with one of Cadence Xcelium simulation tools, Mentor Graphics Questa or Synopsys VCS verification tools.-Basic understanding of Formal verification tools, linting, CDC tools, assertions, functional coverage with covergroups, simulation acceleration and other key verification methodologies.-Working knowledge of protocol BFMs or VIPs for Ethernet / IP, PCIe blocks, AXI etc. Knowledge of IEEE 802.3, Metro Ethernet forum standards, CPRI/eCPRI , ITU-T shall be added plus.-FPGA verification with embedded processors such as RISC-V, ARM or Altera/Intel NIOS processor shall be useful.-Translation of verification testcases towards lab validation with scripts such as PERL/Python- Working knowledge of PC and Unix/Linux operating systems.General ActivitiesCapability to give technical leadership to small team of Verification engineers (mentorship)Independent self-starterStrong commitment to product excellenceExcellent communications skillsCollaboration with stakeholders
Keyskills :
reporting java qlserver systemverilog metroethernet ieee8023 unittesting testcases stronginterpersonalskills problemsolving