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| Job Location | Hyderabad |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | Recruitment Services |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
The Job involves: Development and Implementation of functionality using VHDL / Verilog Verification environment and developing testbenches and functional models Must have atleast two years of experience Verilog or VHDL Sound knowledge of digital electronics and design is essential Experience in PERL scripting is a big plusWorking knowledge of synthesis tools (such as Synopsys Design Compiler , Our Graphics Leanordo Spectrum) is an added advantage Exposure to international industry standards of products design and development is an advantage ,
Keyskills :
scripting erlscripting