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Job Location | Hyderabad |
Education | Not Mentioned |
Salary | Not Disclosed |
Industry | Education / Training |
Functional Area | General / Other SoftwareTesting |
EmploymentType | Full-time |
Responsibilities:Design modules and subsystems, code RTLRun property checking tools, simulations and debugImplement design by performing synthesis, timing closure, lint, CDC, UPFFormal verification of designParticipate in FPGA emulation, FPGA and silicon bring upQualifications:Experience with RTL development, Synthesis, Timing analysis, power analysisExposure to FPGA emulation platforms, silicon bring up, board debugProficient with EDA tools, Python and TclKnowledge of formal methodsBS/MS in EE/CS with 10+ years of experience,
Keyskills :
logic validation verification verilog fpga edatools asicdesign musicmaking timingclosure timinganalysis rtldevelopment formalverification eda rtl cdc lint python design timing sic