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| Job Location | Hyderabad |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | Education / Training |
| Functional Area | General / Other SoftwareTesting |
| EmploymentType | Full-time |
Responsibilities:Develop verification environments for modules, subsystems, top level and FPGABuild models, checkers and random test frameworks using SystemVerilog and UVMParticipate in Low power analysis (UPF), power estimation, C modelingPerform lint, CDC, code coverage, functional coverageFormal verification of modules using SVA assertions. Qualifications:Experience in verifying complex subsystems and ASICsExperience with building scalable verification environments from scratchProficient at Verilog, UVM, EDA tools, scripting, automation, build, regression systems etc.Exposure to FPGA emulation platforms, silicon bring up, board debugBS/MS in EE/CS with 10+ years of experience.,
Keyskills :
uvm ahb apb amba verification edatools asicdesign codecoverage poweranalysis powerestimation formalverification designverification eda cdc fpga lint design verilog sic