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| Job Location | Hyderabad |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | IT - Software |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
5-10 yrs experience BE/BTech Electrical/Electronic or ME/MTech in VLSI design ,>5 yrs of ASIC Synthesis and STA/timing closure experience,Experienced in Synopsys d(Design compiler DC/DC-T/DC-G) Flow.Improving QoR of Synthesized Netlist.Experienced on Synopsys Prime Time tool. Experienced in Hierarchical and flat STA for large SoCs.Define and Debugging of Timing Constraints.Analyze and Fix Timing Issue for lower node Technology, experienced in Multi Mode Multi Corner (MCMM)timing analysis and timing closure nTiming ECO for lower node Technology 40nm, 28nm , 20nm and below.Analyze and Fix Signal Integrity Issue ( Noise & Cross-talk), experienced in Primetime-SI ( PTSI) nKnowledge of Perl Scripting Knowledge of TCL Scripting Knowledge of PCI, USB, DDR interface timing closure.Working closely with Physical design team for timing closure, Roles & Responsibilities:Mandatory Skills: Static Timing analysis, ASIC Synthesis Analog Circuit design, Analog Layout, Analog and Mixed signal Verification Language Skills: English Language
Keyskills :
statictiminganalysisvlsidesigncircuitdesignphysicaldesigntiminganalysissignalintegrityperlscriptingnalogcircuitdesignmixedsignalanaloglayouttimingclosureasicsynthesis