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| Job Location | Hyderabad |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | Consumer Durables / Electronics |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
JOB DESCRIPTION *You will be working with our DFT team from Hyderabad to develop DFT tests. These tests are intended to catch manufacturing defects in targeted IPs inside FPGA/SoC. In this role you will have an opportunity to understand in depth FPGA/SoC silicon architectures, Logic Verification at full chip level, DFT/Testability hooks in Silicon, methods and principles to develop ATPG/Functional test vectors, simulate, debug and generate patterns for production tests.You will work closely with design engineers, Verification engineers and software engineers to ensure FPGA division deploys new products with the highest quality and shortest time to market. Skills will be developed to work on multiple projects supporting key functions within the organization. Good communication and presentation skills are required.Job duties include Generating, verifying and debugging test patterns to test the designs and firmware for new FPGA families. Improving, extending and porting existing manufacturing test designs to all FPGA family members Test specification, plan, and documentationJob RequirementsJOB REQUIREMENTSRequired Skills and Experience BS or MS in EE with 4 to 5 years of experience of working in DFT Hands on experience with industry standard ATPG tools, MBIST, simulation and debugging. Understanding basics of DFT structures, MBIST, Boundary Scan (IEEE 1149.1) Tap Controller Hands-on experience with Verilog behavioral RTL and Gate level netlist. Comfortable with Unix, Perl and/or Shell scripting and familiar with Revision Control (CVS, SVN, ) Strong analytical and problem solving skills Excellent communication, documentation and presentation skills. Must have strong self-learning ability and enjoy working in teams. Preferred Skills Good programming skill/Firmware development skills with C, C++/assembly will be a big plus Exposure to ASIC/FPGA design flow and methodology is a plus (HDL, synthesis, static timing analysis, constraining, Place & Route),
Keyskills :
atpgdftscancoresiliconstatic timing analysiscontinuous improvement facilitationdesign flowboundary scanshell scriptingproblem solvingtiming analysissoftware engineerstest specification