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| Job Location | Hyderabad |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | IT - Software |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
Requirements: The candidate should have knowledge of SOC level verification methodologies and object oriented programming. Understanding and knowledge of Design For Test is desired. Experience: 2 / 3 years of verification exp(DFT DV experience is preferable) Experience in complex SOC verification Good knowledge of Verilog and experience in Verilog simulator and waveform debugging tools , proficiency in debugging both RTL and gate level simulations. Experience with Verilog design and simulation is a must. Candidate preferably should have knowledge in DFT techniques such as JTAG / IEEE standards , MBIST and repair , LBIST , Boundary Scan etc Experienced with testbench creation and functional coverage with HVLs such as System Verilog / Vera Experience with C++ is a plus Good working knowledge of UNIX / Linux and scripting languages (e.g. , cshell , Perl) Team player with strong communication skills Educational Qualification BE / BTech or ME / MTec,