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ENGR STAFF, EDA TOOL_TL

2.00 to 5.00 Years   Hyderabad   21 Nov, 2020
Job LocationHyderabad
EducationNot Mentioned
SalaryNot Disclosed
IndustryConsumer Durables / Electronics
Functional AreaGeneral / Other Software
EmploymentTypeFull-time

Job Description

*As part of the Corporate R&D Design systems technology department, we are responsible for the evaluation, acquisition, development, integration and support of design tools and methodologies towards the worldwide BU development teams. We are looking for a digital RTL2GDS and/or verification specialist that can strengthen our abilities in the digital design space. We are offering a position in our design center in Bucharest to:

  • Influence EDA vendors developments on the features, performance and quality of their digital design tools.
  • Establish new tools and methodologies increasing the quality of ON Semiconductor s products
  • Continuously make proposition to improve EDA tools environment and methodologies in order to improve designer productivity and satisfaction level.
  • Support the worldwide digital design community in using external EDA tools and internally developed scripts.
, *
  • MS Electrical Engineering, Computer Science or related field, or BS with experience.
  • 2-5 years of expertise on Place and Route tools is a must (Cadence Innovus, Synopsys ICC2). Preferably on multi-million gate designs in small node technologies (16nm and smaller) and using Low power design techniques (UPF)
  • Experience with complete digital design flow and design tools (Synthesis, Static Timing Analysis, DFT, Logic Equivalence Checking, ATPG, Place and Route ) from EDA vendors such as Cadence, Mentor, Synopsys
  • Experience with Linux as a user environment
  • Affinity with programming & scripting languages such as Perl, TCL, Python, QT, C, C++, makefiles
  • Having experience with revision controlled development environments (SVN, Cliosoft) is a plus.
  • A team player with excellent communication skills verbal and written
  • Fluent in English.

Keyskills :
static timing analysiseda toolsdesign flowdigital designtiming analysiscomputer sciencecommunication skillsequivalence checkingelectrical engineeringedadftperlatpglinuxpythondesigntcl

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