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FPGA Design

3.00 to 5.00 Years   Hyderabad   09 Jun, 2020
Test and Verification Solutions India Pvt Ltd
Job LocationHyderabad
EducationNot Mentioned
SalaryNot Disclosed
IndustryIT - Software
Functional AreaGeneral / Other Software
EmploymentTypeFull-time

Job Description

  • Master s/Bachelor s degree in Electrical/Electronic engineering with 3-5 years experience in FPGA design/STA
  • Experience with design flows utilizing Unix/Linux, EDA Tools and Verilog/VHDL
  • Very good understanding of timing concepts,
  • Experience in Static Timing Analysis, Delay Calculation, Timing Reporting, Constraints handling
  • Scripting and automation skills in Perl and TCL
  • Candidate must possess passion and commitment for completing projects on time.
  • Candidate must have excellent oral and written communication skills.
  • Understanding of FPGA architectures would be useful.
Location
  • Hyderabad
Experience
  • 3 to 5 years
Package
  • Highly competitive to match experience and capability
,

Keyskills :
statictiminganalysis edatools fpgadesign timinganalysis writtencommunication eda perl unix fpga vhdl linux design timing verilog analysis reporting scripting automation transpromo cl

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