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| Job Location | Hyderabad |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | Consumer Durables / Electronics |
| Functional Area | Hardware / Telecom Equipment DesignNetwork / System Administration |
| EmploymentType | Full-time |
DescriptionAt Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible. Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the worlds first 5G networks, we empower the worlds builders and visionaries whose ideas solve every day problems and enhance peoples lives. If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.Xilinx is looking for a talented individual to join the high speed memory interfaces design engineering group, in the position of Design Engineer to work on development of next generation highly configurable blocks that operate at over 1 GHz data rate. The memory interfaces being developed exceed 6 GHz data rate.The successful candidate will work as a contributing member responsible for the architecture and design of next generation memory interfaces that operate over 6 GHz data rate for Xilinx customers. Responsibilities include RTL development, resolving system level challenges, architecting, implementing, documenting and validating the memory controller IP cores. The area of focus would be on high speed memory interfaces like DDR5, LPDDR5, DDR4, LPDDR4, DDR3, QDR4, LPDDR3 and RLDRAM3. The candidate must have excellent inter-personal and communication skills and be able to work independently.Xilinx holds a strong position in the FPGA all programmable paradigm. This position offers candidates exposure to the latest generation IP, tools, boards, FPGA products and the ability to design and develop high speed memory IP cores. B.E/M.E/M.Tech or B.S/M.S in EE/CE with 6+ years of relevant experience 4+ years of experience in designing complex IP s Excellent Verilog and logic design conceptsExperience with automation using scripting techniques such as PERL, Python or TCLKnowledge of bus protocols like AXI/AHBExcellent waveform debug skills using front end industry standard design tools like VCS, NCSIM, and ModelSim. Excellent communication and problem solving skills.Should have experience working in geographically dispersed team and should be a strong team player,
Keyskills :
hardware designi2c orcadbom debuggingbig data front endlogic design problem solvingrtl