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| Job Location | Hyderabad |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | Consumer Durables / Electronics |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
Physical Design ManagerHands on experience with Implementation (Synthesis, PnR & Signoff) of multimillion gateSoC designs in cutting edge process technologies (40nm, 28nm, 16nm, 10nm) All aspects of Physical Design including Floor Planning, Power Plan, Place and Route,Clock Planning and Clock Tree Synthesis, complex analog IP integration, ParasiticExtraction, Timing Closure, Power / IR Drop (Static and Dynamic), Signal IntegrityAnalysis, Physical Verification (DRC, ERC, LVS), DFM and DFY and Tapeout. Should be able to manage schedules, mentor the juniors and support cross-functionalengineering effort to drive to signoff closure for tapeout Improve design flows to meet the QoR targets and ensure predictability Exposure to the latestdesignrules, processes and innovations need to close PPA on theadvance nodes. Manage a design team of 30-40 engineers working on all aspects of physical designDesired Skills and Experience: B. Tech. / M. Tech. with 10-15 years of experience in Physical Design The candidate should be able to work with and lead a team of engineers on all aspectsof Physical Design tasks on an SOC design Must have prior experience of managing a design team Should have handled RTL to GDS II at Chip level for multiple tape outs Hands-on expertise with technology nodes like 28nm, 16nm and below Good knowledge of EDA tools from Synopsys, Cadence and Mentor, particularly withICCII & Calibre Along with partitioning & budgeting candidate should have hands-on experience inChip/partition floor planning, placement optimizations, bus planning, Clock planning androuting. Good understanding and hands on experience with physical verification(DRC/LVS/ERC/antenna) and other reliability checks(IR/EM/Xtalk) Good understanding of low power implementation techniques and static low powerchecks Hands-on experience in Full chip level signoff STA Being proficient in TCL, Perl scripting is a plus,
Keyskills :
graphicdesign cad mechanical sales tender clocktreesynthesis edatools floorplanning timingclosure physicaldesign physicalverification perlscripting ir ip eda gds soc rtl dfm cl