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IP/SOC SYNTHESIS Engineer

3.00 to 5.00 Years   Hyderabad   09 Jun, 2020
Job LocationHyderabad
EducationNot Mentioned
SalaryNot Disclosed
IndustryIT - Software
Functional AreaGeneral / Other Software
EmploymentTypeFull-time

Job Description

  • Strong knowledge of SOC design methodologies and flows
  • Knowledge of system-level architecture including buses like AXI/AHB
  • Experience with Lint, Synthesis, CDC and STA
  • Work with RTL and DFT engineers, prepare SoC Top/Block level constraints
  • Work closely with SOC Team to achieve full chip timing closure
  • Experience in Formality, ECO process, tool flows and scripting
  • Experience
    • 3-5 Years
    Open Positions
    • 1
    Location
    • Hyderabad
    Package
    • Highly competitive to match experience and capability
    ,

    Keyskills :
    timingclosure dft soc rtl sta eco cdc lint design timing closure scripting synthesis engineers transpromo architecture Primetime ClockTreeSynthesis Timing laceRoute

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