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| Job Location | Hyderabad |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | Recruitment Services |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
As a Physical Design Engineer , the ideal candidate will be responsible for handling all the aspects of Place & Route in RTL to GDSII implementation of complex ASICs using state of the art EDA tools. He should be an effective team player working closely with front end design as well as back end custom layout teams to deliver projects under tight schedule constraints.Required Qualifications: B.S / M.S in Electrical Engineering or related field with 2 - 10 Years of proven track record of independently delivering RTL to GDSII projects. Experience in block & chip level floor planning , power grid design , Place & Route and physical verification. Experience in working with analog IP , hard and soft macros and delivering hierarchical design projects. Experience in Clock Tree Synthesis and Timing Closure Experience in Power / Signal Integrity Analysis Experience with Synopsys RTL to GDSII tool flow is a must. Good scripting skills in C - Shell , Perl & Tcl Must possess good written and verbal communication skills in order to work with teams across the globe,
Keyskills :
planning drc routing verification ip frontenddesign clocktreesynthesis frontend timingclosure physicaldesign signalintegrity communicationskills verbalcommunication lo placeroute electricalengineeri