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| Job Location | Hyderabad |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | Telecom / ISP |
| Functional Area | Service / Installation / Repair |
| EmploymentType | Full-time |
Develop and maintain leading-edge Physical Verification and Extraction flows addressing the needsProven experience with 12nm or below tape out. Familiar with Finfet, Dual Patterning and ULV challenges.Solid understanding, at least at block level but preferably at SoC level of:Gate-level parasitic extraction (with some exposure to transistor-level extraction)Advanced node design rules, process requirements, PDK requirementsHands on experience with block and chip-level physical verification (DRC, LVS, Antenna, XOR, Metalfill)Hands-on experience with Place & Route and understanding of physical DRC fixing and closure methodologiesRunset interpretation and occasional modification/customizationProficiency in Tcl scripting in the context of flow development.Provide layout of test structure sets and custom digital designs in multiple technology nodes while working closely with scribe design and CAD engineers across the globe.Perform layout verifications such as LVS/DRC/DFM/ERC, quality check, and provide accurate and timely documentation to ensure creation of parametric workbook .Creation of schematic design and post layout simulation.Own and support multiple projects in parallel through the Reticle Tapeout flow.Effectively interact and communicate with internal customers to understand the needs and deliver layouts test structures, memory array and custom digital designs.Provide technical leadership and mentor junior staff.The ability to work and communicate effectively in a team and to be able to multi-task effectively in a fast-paced working environment.RequirementsBachelor or higher degree in Electrical/Electronics Engineering.12+ years of relevant experience in the fields of layout design, physical verification or related fields.2 or more years of experience in handling multiple custom IC layout projects.Well versed in schematic design and post layout simulation .Hands on experience with schematic entry, netlist extraction, and post layout verification.Understanding of latch up and antenna effects in layout and their mitigation techniques.Deep expertise in IC layout design tools such as Cadence Virtuoso and physical verification tools such as Calibre, Assura, or ICV.Strong analytical, debug, and problem-solving skills in resolving layout issues related to physical verification and overall layout generation flowFamiliarity with semiconductor electrical fundamentals and device physics.Capable of working in a cross functional and multi-site team environment spanning multiple time zones.Other Desired SkillsDemonstrate good analysis and problem-solving skills. Out-of-the-box thinkingCapability to create scripts to improve layout efficiency and workflow.Experience with custom analog Design and layout is a plus.,
Keyskills :
changing the worldenvironmental impact assessmentic layoutanalog designquality checklayout designproblem solvingcadence virtuosoplaceroute