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Principal Engineer, SQA

15.00 to 17.00 Years   Hyderabad   20 Jun, 2020
Job LocationHyderabad
EducationNot Mentioned
SalaryNot Disclosed
IndustryConsumer Durables / Electronics
Functional AreaQuality (QA-QC)
EmploymentTypeFull-time

Job Description

  • Must be proactive in taking ownership of projects and problems, willing to take on challenging projects and open to creative solutions
  • Must be motivated to drive delivery and support of robust, high quality software
  • Test and enhance existing software test flows using system-level testing of existing and new Microsemi FPGA features of Libero SoC flows
  • Should have hands on Experience in Design Creation, Synthesis and simulations
  • Experience in timing closure and HW testing and debugging will be a plus
  • Experience in working with Arm processors is a plus. Any exposure to a high speed protocol like Pcie, DDR will be a plus
  • Should be able to provide feedback on FPGA SW functionality, , use cases, tools, and documentation
  • Good experience with different FPGA tools like Vivado, Ise and Quartus will be a plus
  • Need to work with multiple cross-functional and global teams. Should be able to mentor, lead /coach junior members of team. Should be able to Manage priorities, track tasks and communicate status
Job Requirements
  • Bachelors/Master s Degree Electrical Engineering
  • At least 15+ years of experience with FPGA flows, FPGA architectures, Synthesis, Timing closure techniques
  • Strong design and debugging skills
  • Proficiency in VHDL and/or Verilog. Proficiency in running behavioral, post-synthesis and/or post-layout simulations
  • Storing experience working in a Linux environment, Perl, and TCL scripting is a must
  • Understanding of FPGA architectures is a plus
  • Knowledge of competitive tools would be of advantage
  • Strong communication skills
,

Keyskills :
java linux javascript framework usecases timingclosure arm soc ise ddr perl fpga vhdl pcie design timing testing closure cl

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